This invention relates to methods of forming conductive lines, such as co-axial lines, and to integrated circuitry incorporating conductive lines.
As the density of integrated circuitry (IC) devices increases, continuing challenges are posed to find interconnect structures which are suitable for use with such densely-packed IC devices. For example, as clock cycles increase, interconnect structures which are capable of handling such clock cycles become necessary. Further, such interconnect structures must overcome concerns associated with signal propagation times, crosstalk, increased system noise and other spurious electrical effects which are detrimental to the performance of integrated circuits.
This invention arose out of concerns associated with providing integrated circuitry interconnect structures which are suitable for use with densely-packed, high-speed integrated circuitry devices.
Conductive lines, such as co-axial lines, integrated circuitry incorporating such conductive lines, and methods of forming the same are described. In one aspect, a substrate having an outer surface is provided. A masking material is formed over the outer surface and subsequently patterned to form a conductive line pattern. An inner conductive layer is formed within the conductive line pattern, followed by formation of a dielectric layer thereover and an outer conductive layer over the dielectric layer. Preferred implementations include forming the inner conductive layer through electroplating, or alternatively, electroless plating techniques. Other preferred implementations include forming the dielectric layer from suitable polymer materials having desired dielectric properties. A vapor-deposited dielectric layer of parylene is one such preferred dielectric material.